1. Technical Field
The present disclosure relates to a semiconductor integrated circuit, and a latch circuit and flip-flop circuit including the semiconductor integrated circuit.
2. Description of the Related Art
A large number of latch circuits and flip-flop circuits are used in semiconductor integrated circuits. The widespread use of mobile devices has led to growing demand for semiconductor integrated circuits that consume less power, and reductions in power consumption of latch circuits and flip-flop circuits have been increasingly desired.
Typically, to reduce the power consumption of a latch circuit or flip-flop circuit, it is desirable to minimize the number of transistors on the clock signal propagation path. For example, writing a data signal to a latch is eased if there is a mechanism of temporarily interrupting a latch feedback signal according to a clock signal. On the other hand, the number of transistors on the clock signal propagation path can be reduced by omitting a control switch that serves as such an interruption mechanism.
For example, Patent Literature (PTL) 1 (Japanese Patent Publication No. 3572700 (FIG. 3)) and PTL 2 (the specification of U.S. Pat. No. 6,008,678) disclose the techniques of, in each of a master latch circuit and a slave latch circuit constituting a flip-flop circuit, omitting the above-mentioned control switch and generating a latch feedback signal only by an inverter.